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w25q32 jv publication release date: august 30 , 2016 - revision c 3v 32 m - bit serial flash memory with dual , quad spi
w25q32 jv - 1 - table of contents 1. general descriptions ................................ ................................ ................................ ............. 4 2. features ................................ ................................ ................................ ................................ ....... 4 3. package types and pi n configurations ................................ ................................ .......... 5 3.1 pin configuration soic 208 - mil / vsop 208 - mil ................................ ................................ . 5 3.2 pad configuration wson 6x5 - mm, xson 4x4 - mm ................................ ............................ 5 3.3 pin description soic / vsop 208 - mil, wson 6x5 - mm, xson 4x4 - mm ............................ 5 3.4 pin configuration soic 300 - mil ................................ ................................ ........................... 6 3.5 pin description soic 300 - mil ................................ ................................ ............................... 6 3.6 ball configuration tfbga 8x6 - mm (6x4 ball array) ................................ ............................ 7 3.7 ball description tfbga 8x6 - mm ................................ ................................ ......................... 7 3.8 pin configuration pdip 300 - mil ................................ ................................ ............................ 8 3.9 pin description pdip 300 - mil ................................ ................................ ............................... 8 4. pin descriptions ................................ ................................ ................................ ........................ 9 4.1 chip select (/cs) ................................ ................................ ................................ .................. 9 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) ................................ .... 9 4.3 serial clock (clk) ................................ ................................ ................................ ................ 9 4.4 reset (/reset) ................................ ................................ ................................ .................... 9 5. block diagram ................................ ................................ ................................ .......................... 10 6. functional descripti ons ................................ ................................ ................................ ..... 11 6.1 standard spi instructions ................................ ................................ ................................ ... 11 6.2 dual spi instructions ................................ ................................ ................................ .......... 11 6.3 quad spi instructions ................................ ................................ ................................ ......... 11 6. 4 software reset & hardware /reset pin ................................ ................................ ........... 11 6.5 write protection ................................ ................................ ................................ .................. 12 write protect features ................................ ................................ ................................ .......... 12 7. status and configura tion registers ................................ ................................ ............ 13 7.1 status registers ................................ ................................ ................................ ................. 13 erase/write in progress (busy) C status only ................................ ................................ . 13 write enable latch (wel) C status only ................................ ................................ ........... 13 block protect bits (bp2, bp1, bp0) C volatile/non - volatile writable ................................ . 13 top/bottom block protect (tb) C volatile/non - volatile writable ................................ ........ 14 sector/block protect bit (sec) C volatile/non - volatile writable ................................ ........ 14 complement protect (cmp) C volatile/non - volatile writable ................................ ............ 14 status register protect ( sr l ) ................................ ................................ ............................... 15 erase/program suspend status (sus) C status only ................................ ....................... 15 security register lock bits (lb3, lb2, lb1) C volatile/non - volatile otp writable ........... 15 quad enable ( qe ) C volatile/non - volatile writable ................................ ......................... 16 write protect selection (wps) C volatile/non - volatile writable ................................ ...... 16 output driver strength (drv1, drv0) C volatile/non - volatile writable .......................... 16 reserved bits C non functional ................................ ................................ ...................... 16 status register memory protection (wps = 0, cmp = 0) ................................ ................... 17
w25q32 jv publication release date: august 30 , 2016 - 2 - revision c status register memory protection (wps = 0, cmp = 1) ................................ ................... 18 individual block memory pro tection (wps=1) ................................ ................................ .... 19 8. instructions ................................ ................................ ................................ ............................. 20 8.1 device id and instruction set tables ................................ ................................ ................. 20 manufacturer and device identification ................................ ................................ ................. 20 instruction set table 1 (standard spi instructions) (1) ................................ ........................... 21 instruction set table 2 (dual/quad spi instructions) (1) ................................ ......................... 22 8.2 instruction descriptions ................................ ................................ ................................ ...... 23 write enable (06h) ................................ ................................ ................................ ................ 23 write enable for volatile status register (50h) ................................ ................................ ..... 23 write disable (04h) ................................ ................................ ................................ ............... 24 read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) ............... 24 write status register - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) ............... 25 read data (03h) ................................ ................................ ................................ ................... 27 fast read (0bh) ................................ ................................ ................................ ................... 28 fast read dual output (3bh) ................................ ................................ ............................... 29 fast read quad output (6bh) ................................ ................................ .............................. 30 f ast read dual i/o (bbh) ................................ ................................ ................................ ... 31 fast read quad i/o (ebh) ................................ ................................ ................................ .. 32 set burst with wrap (77h) ................................ ................................ ................................ ... 33 page program (02h) ................................ ................................ ................................ ........... 34 quad input page program ( 3 2h) ................................ ................................ ......................... 35 sector erase (20h) ................................ ................................ ................................ .............. 36 32kb block erase (52h) ................................ ................................ ................................ ...... 37 64kb block erase (d8h) ................................ ................................ ................................ ..... 38 chip erase (c7h / 60h ) ................................ ................................ ................................ ....... 39 erase / program suspend (75h) ................................ ................................ ......................... 40 erase / program resume (7ah) ................................ ................................ .......................... 41 power - down (b9h) ................................ ................................ ................................ .............. 42 release power - down / device id (abh) ................................ ................................ ............. 43 read manufacturer / device id (90h) ................................ ................................ ................. 44 read manufacturer / device id dual i/o (92h) ................................ ................................ ... 45 read manufacturer / device id quad i/o (94h) ................................ ................................ .. 46 read unique id number (4bh) ................................ ................................ ........................... 47 read jedec id (9fh) ................................ ................................ ................................ ........ 48 read sfdp register (5ah) ................................ ................................ ................................ . 49 erase security registers (44h) ................................ ................................ ........................... 50 program security registers (42h) ................................ ................................ ....................... 51 read security registers (48h) ................................ ................................ ............................ 52 individual block/sector lock (36h) ................................ ................................ ...................... 53 individual block/sector unlock (39h) ................................ ................................ .................. 54 read block/sector lock (3dh) ................................ ................................ ............................ 55 global block/sector lock (7eh) ................................ ................................ .......................... 56 global block/sector unlock (98h) ................................ ................................ ....................... 56 enable reset (66h) and reset device (99h) ................................ ................................ ...... 57
w25q32 jv - 3 - 9. electrical character istics ................................ ................................ ............................... 58 9.1 absolute maximum ratings (1) ................................ ................................ .......................... 58 9.2 operating ranges ................................ ................................ ................................ .............. 58 9.3 power - up power - down timing and requirements ................................ ........................... 59 9.4 dc electrical characteristics - ................................ ................................ ............................. 60 9.5 ac measurement conditions ................................ ................................ ............................. 61 9.6 ac electrical characteristics (6) ................................ ................................ ........................... 62 9.7 serial output timing ................................ ................................ ................................ ........... 64 9.8 serial input timing ................................ ................................ ................................ .............. 64 10. package specificatio ns ................................ ................................ ................................ ....... 65 10.1 8 - pin soic 208 - mil (package code ss) ................................ ................................ ............ 65 10.2 8 - pin vsop 208 - mil (package code st) ................................ ................................ ........... 66 10.3 8 - pad wson 6x5 - mm (package code zp) ................................ ................................ ....... 67 10.4 pad xson 4x4x0.45 - mm (package code xg) ................................ ................................ .. 68 10.5 16 - pin soic 300 - mil (package code sf) ................................ ................................ .......... 69 10.6 8 - pin pdip 300 - mil (package code da) ................................ ................................ ............ 70 10.8 24 - ball tfbga 8x6 - mm (package code tc, 6x4 ball array) ................................ ............. 71 11. ordering information ................................ ................................ ................................ .......... 73 11.1 valid part numbers and top side marking ................................ ................................ ........ 74 12. revision history ................................ ................................ ................................ ...................... 75
w25q32 jv publication release date: august 30 , 2016 - 4 - revision c 1. general descriptions the w25q32 jv (32m - bit) serial flash memory provides a storage solution for systems with limited space, pins and power. the 25q series offers flexibility and performance well beyond ordinary serial flash devices. they are ideal for code shadowing to ram, executing code directly from d ua l/quad spi (xip) and storing voice, text and data. the device operates on 2. 7 v to 3.6v power supply with current consumption as low as 1a for power - down. the w25q32 jv array is organized into 16,384 programmable pages of 256 - bytes each. up to 256 bytes can be programmed at a time. pages can be erased in groups of 16 (4kb sector erase), groups of 128 (32kb block erase), groups of 256 (64kb block erase) or the entire chip (chip erase). the w25q32 jv has 1,024 erasable sectors and 64 erasable blocks respectively. the small 4kb sectors allow for greater flexibility in applications that require data and parameter storage. (see figure 2.) the w25q32 jv supports the standard ser ial peripheral interface (spi), and a high performance dual/quad output as well as dual/quad i/o spi: serial clock, chip select, serial data i/o0 (di), i/o1 (do), i/o2, and i/o3. spi clock frequencies of up to 133mhz are supported allowing equivalent clock rates of 266mhz ( 133mhz x 2) for dual i/o and 532mhz ( 133mhz x 4 ) for quad i/o when using the fast read dual/quad i/o instructions. these transfer rates can outperform standard asynchronous 8 and 16 - bit parallel flash memories. additionally, the device s upports jedec standard manufacturer and device id and sfdp register, a 64 - bit unique serial number and three 256 - bytes security registers. 2. features ? new family of spiflash memories C C C 0 , io 1 C 0 , io 1 , io 2 , io 3 C (1) ? highest performance serial flash C C C C C ? efficient continuous read C C C C ? low power, wide temperature range C C C ? flexible architecture with 4kb sectors C C C ? advanced security features C C ( 2 ) C C C C C C ? space efficient packaging C C C C C C C note : 1. hardware /reset pin is only available on soic - 16 & tfbga package s 2. please contact winbond for details.
w25q32 jv - 5 - 3. p a cka ge types and pin con figurations 3.1 pin configuration soic 208 - mil / vsop 208 - mil figure 1a. w25q32jv pin assignments, 8 - pin soic / vsop 208 - mil (package code ss / st) 3.2 pad configuration wson 6x5 - mm , xson 4x4 - mm figure 1 b. w25q32jv pad assignm ents, 8 - pad wson 6x5 - mm (package code zp , xg ) 3.3 pin description soic / vsop 208 - mil, wson 6x5 - mm , xson 4x4 - mm pad no. pad name i/o function 1 /cs i chip select input 2 do (io1) i/ o data output ( data input output 1) (1) 3 io2 i /o data input output 2 (2) 4 gnd ground 5 di (io0) i/o data input ( data input output 0) (1) 6 clk i serial clock input 7 io3 i /o data input output 3 (2) 8 vcc power supply notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions . 1 2 3 4 8 7 6 5 /cs do (io 1 ) io 2 gnd vcc io3 di (io 0 ) clk top view
w25q32 jv publication release date: august 30 , 2016 - 6 - revision c 3.4 pin configuration soic 300 - mil figure 1c. w25q32jv pin assignments, 16 - pin soic 300 - mil (package code sf) 3.5 pin description soic 300 - mil pin no. pin name i/o function 1 io3 i /o data input output 3 (2) 2 vcc power supply 3 /reset i reset input (3) 4 n/c no connect 5 n/c no connect 6 n/c no connect 7 /cs i chip select input 8 do (io1) i/ o data output (data input output 1) (1) 9 io2 i /o data input output 2 (2) 10 gnd ground 11 n/c no connect 12 n/c no connect 13 n/c no connect 14 n/c no connect 15 di (io0) i /o data input (data input output 0) (1) 16 clk i serial clock input notes: 1. io0 and io1 are used for standard and dual spi instructions . 2. io0 C io3 are used for quad spi instructions. 3. the /reset pin is a dedicated hardware reset pin regardless of device settings or operation states . if the hardware reset function is not used, this pin can be left floating or connected to vcc in the system. 1 2 3 4 / c s d o ( i o 1 ) i o 2 g n d v c c i o 3 d i ( i o 0 ) c l k t o p v i e w n c / r e s e t n c n c n c n c n c n c 5 6 7 8 1 0 9 1 1 1 2 1 3 1 4 1 5 1 6
w25q32 jv - 7 - 3.6 ball configuration tfbga 8x6 - mm ( 6x4 ball array) figure 1d. w25q32jv ball assignments, 24 - ball tfbga 8x6 - mm (package code tc) 3.7 ball description tfbga 8x6 - mm ball no. pin name i/o function a4 /reset i reset input (3) b2 clk i serial clock input b3 gnd ground b4 vcc power supply c2 /cs i chip select input c4 io2 i /o data input output 2 (2) d2 do (io1) i/ o data output (data input output 1) (1) d3 di (io0) i /o data input (data input output 0) (1) d4 io3 i /o data input output 3 (2) multiple nc no connect notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions. 3. the /reset pin is a dedicated hardware reset pin regardless of device settings or operation states . if the hardware reset function is not used, this pin can be left floating or connected to vcc in the syste m
w25q32 jv publication release date: august 30 , 2016 - 8 - revision c 3.8 pin configuration pdip 300 - mil figure 1e. w25q32jv pin assignments, 8 - pin pdip (package code da) 3.9 pin description pdip 300 - mil pad no. pad name i/o function 1 /cs i chip select input 2 do (io1) i/ o data output ( data input output 1) (1) 3 io2 i /o data input output 2 (2) 4 gnd ground 5 di (io0) i/o data input ( data input output 0) (1) 6 clk i serial clock input 7 io3 i /o data input output 3 (2) 8 vcc power supply notes: 1. io0 and io1 are used for standard and dual spi instructions 2. io0 C io3 are used for quad spi instructions. 1 2 3 4 8 7 6 5 / cs do(io 1 ) io 2 gnd vcc io 3 di(io 0 ) clk top view
w25q32 jv - 9 - 4. pin descriptions 4.1 chip select (/cs) the spi chip select (/cs) pin enables and disables device operation. when /cs is high the device is deselected and the serial data output (do, or io0, io1, io2, io3) pins are at high impedance. when deselected, the devices power consumption will be at standby levels unless an internal erase, program or wr ite status register cycle is in progress. when /cs is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power - up, /cs must transition from high to low before a new instruction will be accepted. the /cs input must track the vcc supply level at power - up and power - down (see write protection and figure 58). if needed a pull - up resister on the /cs pin can be used to accomplish this. 4.2 serial data input, output and ios (di, do and io0, io1, io2, io3) the w25q32jv supports s tandard spi, dual spi and quad spi operation in each individual stacked die . all 8 - bit instructions are shifted into the device through di (io0) pin, address and data are shifted in and out of the device through either di & do pins for standard spi instructions, io0 & io1 pins for dual spi instructions, or io0 - io3 pins for quad spi instructions. 4.3 serial clock (clk) the spi serial clock input (clk) pin provides the tim ing for serial input and output operations. ("see spi operations") 4.4 reset (/reset) (1) a dedicated hardware /reset pin is available on soic - 16 and tfbga packages. when its driven low for a minimum period of ~1s, this device will terminate any external or inter nal operations and return to its power - on state. note: 1. hardware /reset pin is available on soic - 16 or tfbga; please contact winbond for this package.
w25q32 jv publication release date: august 30 , 2016 - 10 - revision c 5. block diagram figure 2. w25q32jv serial flash memory block diagram
w25q32 jv - 11 - 6. functional descripti ons 6.1 standard spi instructions the w25q32jv is accessed through an spi compatible bus consisting of four signals: serial clock (clk), chip select (/cs), serial data input (di) and serial data output (do). standard spi instructions use the di input pin to serial ly write instructions, addresses or data to the device on the rising edge of clk. the do output pin is used to read data or status from the device on the falling edge of clk. spi bus operation mode 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3 concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0, the clk signal is normally low on the falling and rising edges of /cs. for mode 3, the clk signal is normally high on the falling and rising edges of /cs. 6.2 dual spi instructions the w25q32jv supports dual spi operation when using instructions such as fast read dual output (3bh) and fast read dual i/o (bbh). these instructions all ow data to be transferred to or from the device at two to three times the rate of ordinary serial flash devices. the dual spi read instructions are ideal for quickly downloading code to ram upon power - up (code - shadowing) or for executing non - speed - critical code directly from the spi bus (xip) . when using dual spi instructions, the di and do pins become bidirectional i/o pins: io0 and io1. 6.3 quad spi instructions the w25q32jv supports quad spi operation when using instructions such as fast read quad output (6 bh), and fast read quad i/o (ebh). these instructions allow data to be transferred to or from the device four to six times the rate of ordinary serial flash. when using quad spi instructions , the di and do pins become bidirectional io0 and io1, with the additional i/o pins: io2, io3 . 6.4 software reset & hardware /reset pin the w25q32jv can be reset to the initial power - on state by a software reset se quence. this sequence must include two consecutive instruction s: enable reset (66h) & reset (99h). if the ins truction sequence is successfully accepted, the device will take approximately 30 s ( t rst ) to reset. no instruction will be accepted during the reset period. for the soic - 16 and tfbga package s , w25q32jv provides a dedicated hardware /reset pin. drive the /reset pin low for a minimum period of ~ 1s (treset*) will interrupt any on - going external/internal operations and reset the device to its initial power - on state. hardware /reset pin has high er prior ity than other spi input signals (/cs, clk, ios). note: 1. hardware /reset pin is available on soic - 16 or tfbga; please contact winbond for his package. 2. while a faster /reset pulse (as short as a few hundred nanoseconds) will often reset the device, a 1us minimum is recommended to ensure reliable operation. 3. there is an internal pull - up resistor for the dedicated /reset pin on the soic - 16 package. if the reset function is not needed, this pin can be left floating in the system .
w25q32 jv publication release date: august 30 , 2016 - 12 - revision c 6.5 write protection applications that use non - volatile memory must take into consideration the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern, the w25q32jv provides several means to protect the data from inadvertent writes. write protect features ? device resets wh en vcc is below threshold ? time delay write disable after power - up ? write enable/disable instructions and automatic write disable after erase or program ? software write protection using status registers ? additional individual block/sector locks for array prote ction ? write protection using power - down instruction ? lock down write protection for status register until the next power - up ? one time program (otp) write protection for array and security registers using status register * * note: this feature is available up on special order. please contact winbond for details. upon power - up or at power - down, the w25q32jv will maintain a reset condition while vcc is below the threshold value of v wi , (see power - up timing and voltage levels and figure 43). while reset, all oper ations are disabled and no instructions are recognized. during power - up and after the vcc voltage exceeds v wi , all program and erase related instructions are further disabled for a time delay of t puw . this includes the write enable, page program, sector er ase, block erase, chip erase and the write status register instructions. note that the chip select pin (/cs) must track the vcc supply level at power - up until the vcc - min level and t vsl time delay is reached, and it must also track the vcc supply level at power - down to prevent adverse command sequence. if needed a pull - up resister on /cs can be used to accomplish this. after power - up the device is automatically placed in a write - disabled state with the status register write enable latch (wel) set to a 0. a write enable instruction must be issued before a page program, sector erase, block erase, chip erase or write status register instruction will be accepted. after completing a program, erase or write instruction the write enable latch (wel) is automaticall y cleared to a write - disabled state of 0. software controlled write protection is facilitated using the write status register instruction and setting the status register protect ( srl ) and block protect (cmp , sec, tb, bp[2:0]) bits. these settings allow a p ortion or the entire memory array to be configured as read only. the w25q32jv also provides another write protect method using the individual block locks. each 64kb block (except the top and bottom blocks, total of 62 blocks) and each 4kb sector within th e top/bottom blocks (total of 32 sectors) are equipped with an individual block lock bit. when the lock bit is 0, the corresponding sector or block can be erased or programmed; when the lock bit is set to 1, erase or program commands issued to the correspo nding sector or block will be ignored. when the device is powered on, all individual block lock bits will be 1, so the entire memory array is protected from erase/program. an individual block unlock (39h) instruction must be issued to unlock any specific sector or block. the wps bit in status register - 3 is used to decide which write protect scheme should be used. when wps=0 (factory default), the device will only utilize cmp, sec, tb, bp[2:0] bits to protect specific areas of the array; when wps=1, the de vice will utilize the individual block locks for write protection.
w25q32 jv - 13 - 7. status and configura tion registers three status and configuration registers are provided for w25 q16jv . the read status register - 1/2/3 instructions can be used to provide status on the availability of the flash memory array, whether the device is write enabled or disabled, the state of write protection, quad spi setting, security register lock status, erase/program suspend status, and output driver strength. the write status register ins truction can be used to configure the device write protection features, quad spi setting, security register otp locks, and output driver strength. write access to the status register is controlled by the state of the non - volatile status register protect bi ts ( srl ), the write enable instruction, and durin g standard/dual spi operations. 7.1 status registers figure 4 a . status register - 1 erase/write in progress (busy) C status only busy is a read only bit in the status register (s0) that is set to a 1 state when the device is executing a page program, quad page program, sector erase, block erase, chip erase, write status register or erase/program security register instruction. during this time the device will ignore further instructions except for the read status register and erase/program suspend instruction (see t w , t pp , t se , t b e , and t ce in ac characteristics). when the program, erase or write status/security register instruction h as completed, the busy bit will be cleared to a 0 state indicating the device is ready for further instructions. write enable latch (wel) C status only write enable latch (wel) is a read only bit in the status register (s1) that is set to 1 after executin g a write enable instruction. the wel status bit is cleared to 0 when the device is write disabled. a write disable state occurs upon power - up or after any of the following instructions: write disable, page program, quad page program, sector erase, block e rase, chip erase, write status register, erase security register and program security register. block protect bits (bp2, bp1, bp0) C volatile/non - volatile writable the block protect bits (bp2, bp1, bp0) are non - volatile read/write bits in the status regist er (s4, s3, and s2) that provide write protection control and status. block protect bits can be set using the write status register instruction (see t w in ac characteristics). all, none or a portion of the memory array can be protected from program and era se instructions (see status register memory protection table). the factory default setting for the block protection bits is 0, none of the array protected. srp sec tb bp 2 bp 1 bp 0 wel busy top / bott om protect write enable latch s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 status r egister protect sector protect block protect bit s erase / write in progress ( volatile ) ( non - volatile ) ( non - volatile ) ( non - volatile ) ( non - volatile )
w25q32 jv publication release date: august 30 , 2016 - 14 - revision c top/bottom block protect (tb) C volatile/non - volatile writable the non - volatile top/bottom bit (tb) controls if the block protect bits (bp2, bp1, bp0) protect from the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the factory default setting is tb=0. the tb bit can be set with the write status regi ster instruction depending on the state of the srl and wel bits. sector /block protect bit (sec) C volatile/non - volatile writable the non - volatile sector /block p rotect bit (sec) controls if the block protect bits (bp2, bp1, bp0) protect either 4kb sectors (sec=1) or 64kb blocks (sec=0) in the top (tb=0) or the bottom (tb=1) of the array as shown in the status register memory protection table. the default setting is sec =0. complement protect (cmp) C volatile/non - volatile writable the complement protect bit (cmp) is a non - volatile read/write bit in the status register (s14). it is used in conjunction with sec, tb, bp2, bp1 and bp0 bits to provide more flexibility for the array protection. once cmp is set to 1, previous array protection set by sec, tb, bp2, bp1 and bp0 will be reversed. for instance, when cmp=0, a top 64kb block can be protected while the rest of the array is not; when cmp=1, the top 64kb block will become unprotected while the rest of the array become read - only. please refer to the status register memory protection table for details. the default setting is cmp =0.
w25q32 jv - 15 - status register protect ( sr l ) the status register lock bit (srl) is a volatile/non - volatile read/write bit in the status register (s8) . the srl bit controls the method of write protection to the status registers : temporary power lock - down or permanently one time p rogram otp . srl status register lock description 0 non - lock status register s are unlocked . 1 power lock - down ( t emporary/volatile) status register s are locked and cannot be written to until the next power - down, power - up cycle to reset srl=0 . one time program ( 1 ) (permanently/non - volatile) a special instruction flow can be used to permanently otp lock the status registers. note: 1 . please contact winbond for details regarding the special instruction sequence. figure 4 b . status register - 2 erase/program suspend status (sus) C status only the suspend status bit is a read only bit in the status register (s15) that is set to 1 after executing a erase/program suspend (75h) instruction. the sus status bit is cleared to 0 by erase/program resume (7ah) instruction as well as a power - down, power - up cycle. security register lock bits (lb3, lb2, lb1) C volatile/non - volatile otp writable the security re gister lock bits (lb3, lb2, lb1) are non - volatile one time program (otp) bits in status register (s13, s12, s11) that provide the write protect control and status to the security registers. the default state of lb3 - 1 is 0, security registers are unlocked. lb3 - 1 can be set to 1 individually using the write status register instruction. lb3 - 1 are one time programmable (otp), once its set to 1, the corresponding 256 - byte security register will become read - only permanently. s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 sus cmp lb 3 lb 2 lb 1 ( r ) qe sr l s tatus register lock ( volatile / non - volatile writable ) complement protect ( volatile / non - volatile writable ) security register lock bits ( volatile / non - volatile otp writable ) reserved quad enable ( volatile / non - volatile writable ) suspend status ( status - only )
w25q32 jv publication release date: august 30 , 2016 - 16 - revision c quad enable ( qe ) C volatile/non - volatile writable the quad enable (qe ) bit is a non - volatile read/write bit in the status register (s 9 ) that allows quad spi . when the qe bit is set to a 0 state (factory default for part numbers with ordering options im ), the /wp pin and /h old are enabled. when the qe bit is set to a 1(factory default for quad enabled part numb ers with ordering option iq), the quad io2 and io3 pins are enabled, and /wp and /hold functions are disabled. warning: if the io2 or io3 pins are tied directly to t he power supply or ground during standard spi or dual spi operation, the qe bit should never be set to a 1. figure 4 c . status register - 3 write protect selection (wps) C volatile/non - volatile writable the wps bit is used to select which write protect scheme should be used. when wps=0, the device will use the combination of cmp, sec, tb, bp[2:0] bits to protect a specific area of the memory array. when wps=1, the device will utilize the individual block locks to protect any individual sector or blocks. the default value for all individual block lock bits is 1 upon device power on or after reset. output driver strength (drv1, drv0) C volatile/non - volatile writable the drv1 & drv0 bits are used to determine the output driver strength for the read operations. drv1, drv0 driver strength 0, 0 100% 0, 1 75% 1, 0 50% 1, 1 25% (default) reserved bits C non functional there are a few reserved status register bits that may be read out as a 0 or 1. it is recommended to ignore the values of those bits. during a write status register instruction, the reserved bits can be written as 0, but there will not be any effects. s 16 drv 1 drv 2 re served s 17 s 19 s 20 s 21 s 22 s 23 s 18 wps ( r ) re served re served output d river st rengt h ( volatile / no n - volatile writable ) write protect selection ( volatile / no n - volatile writable ) re served ( r ) ( r ) ( r ) ( r )
w25q32 jv - 17 - status register memory protection (wps = 0, cmp = 0) status register (1) w25q32 j v (32m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 none none none none 0 0 0 0 1 63 3f0000h C 3fffffh 64kb upper 1/64 0 0 0 1 0 62 and 63 3e0000h C 3fffffh 128kb upper 1/32 0 0 0 1 1 60 thru 63 3c0000h C 3fffffh 256kb upper 1/16 0 0 1 0 0 56 thru 63 380000h C 3fffffh 512kb upper 1/8 0 0 1 0 1 48 thru 63 300000h C 3fffffh 1mb upper 1/4 0 0 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 0 1 0 0 1 0 000000h C 00ffffh 64kb lower 1/64 0 1 0 1 0 0 and 1 000000h C 01ffffh 128kb lower 1/32 0 1 0 1 1 0 thru 3 000000h C 03ffffh 256kb lower 1/16 0 1 1 0 0 0 thru 7 000000h C 07ffffh 512kb lower 1/8 0 1 1 0 1 0 thru 15 000000h C 0fffffh 1mb lower 1/4 0 1 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 x x 1 1 1 0 thru 63 000000h C 3f ffffh 4mb all 1 0 0 0 1 63 3ff000 h C 3f ffffh 4kb u - 1/1024 1 0 0 1 0 63 3fe000 h C 3f ffffh 8kb u - 1/512 1 0 0 1 1 63 3fc000 h C 3f ffffh 16kb u - 1/256 1 0 1 0 x 63 3f8000 h C 3f ffffh 32kb u - 1/128 1 1 0 0 1 0 000000h C 000fffh 4kb l - 1/1024 1 1 0 1 0 0 000000h C 001fffh 8kb l - 1/512 1 1 0 1 1 0 000000h C 003fffh 16kb l - 1/256 1 1 1 0 x 0 000000h C 007fffh 32kb l - 1/128 notes: 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored.
w25q32 jv publication release date: august 30 , 2016 - 18 - revision c status register memory protection (wps = 0, cmp = 1) status register (1) w25q32 j v (32m - bit) memory protecti on (3) sec tb bp2 bp1 bp0 protected block(s) protected addresses protected density protected portion (2) x x 0 0 0 0 thru 63 000000h C 3fffffh 4mb all 0 0 0 0 1 0 thru 62 000000h C 3effffh 4,032kb lower 63/64 0 0 0 1 0 0 and 61 000000h C 3dffffh 3,968kb lower 31/32 0 0 0 1 1 0 thru 59 000000h C 3bffffh 3,840kb lower 15/16 0 0 1 0 0 0 thru 55 000000h C 37ffffh 3,584kb lower 7/8 0 0 1 0 1 0 thru 47 000000h C 2fffffh 3mb lower 3/4 0 0 1 1 0 0 thru 31 000000h C 1fffffh 2mb lower 1/2 0 1 0 0 1 1 thru 63 010000h C 3fffffh 4,032kb upper 63/64 0 1 0 1 0 2 and 63 020000h C 3fffffh 3,968kb upper 31/32 0 1 0 1 1 4 thru 63 040000h C 3fffffh 3,840kb upper 15/16 0 1 1 0 0 8 thru 63 080000h C 3fffffh 3,584kb upper 7/8 0 1 1 0 1 16 thru 63 100000h C 3fffffh 3mb upper 3/4 0 1 1 1 0 32 thru 63 200000h C 3fffffh 2mb upper 1/2 x x 1 1 1 none none none none 1 0 0 0 1 0 thru 63 000 000 h C 3f efffh 4,092 kb l - 1023/1024 1 0 0 1 0 0 thru 63 000 000 h C 3f dfffh 4,08 8kb l - 511/512 1 0 0 1 1 0 thru 63 000 000 h C 3f bfffh 4,080 kb l - 255/256 1 0 1 0 x 0 thru 63 000 000 h C 3f 7fffh 4,064 kb l - 127/128 1 1 0 0 1 0 thru 63 00 1 000h C 3ff fffh 4,092 kb u - 1023/1024 1 1 0 1 0 0 thru 63 00 2 000h C 3ff fffh 4,08 8kb u - 511/512 1 1 0 1 1 0 thru 63 00 4 000h C 3ff fffh 4,080 kb u - 255/256 1 1 1 0 x 0 thru 63 00 8 000h C 3ff fffh 4,064 kb u - 127/128 notes: 1. x = dont care 2. l = lower; u = upper 3. if any erase or program command specifies a memory region that contains protected data portion, this command will be ignored .
w25q32 jv - 19 - individual block memory protection (wps=1) figure 4 d . individual block/sector locks notes: 1. individual block/sector protection is only valid when wps=1. 2. all individual block/sector lock bits are set to 1 by default after power up, all memory array is protected. s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 1 ( 6 4 k b ) b l o c k 6 2 ( 6 4 k b ) s e c t o r 0 ( 4 k b ) s e c t o r 1 ( 4 k b ) s e c t o r 1 4 ( 4 k b ) s e c t o r 1 5 ( 4 k b ) b l o c k 0 ( 6 4 k b ) b l o c k 6 3 ( 6 4 k b ) i n d i v i d u a l b l o c k l o c k s : 3 2 s e c t o r s ( t o p / b o t t o m ) 6 2 b l o c k s i n d i v i d u a l b l o c k l o c k : 3 6 h + a d d r e s s i n d i v i d u a l b l o c k u n l o c k : 3 9 h + a d d r e s s r e a d b l o c k l o c k : 3 d h + a d d r e s s g l o b a l b l o c k l o c k : 7 e h g l o b a l b l o c k u n l o c k : 9 8 h
w25q32 jv publication release date: august 30 , 2016 - 20 - revision c 8. instructions the standard/dual/quad spi instruction set of the w25q32jv consists of 48 basic instructions that are fully controlled through the spi bus (see instruction set table1 - 2). instructions are initiated with the falling edge of chip select (/cs). the first byte of data clocked into the di input provides the instruction code. data on the di input is sampled on the rising edge of clock with most significant bit (msb) first. instructions vary in length from a single byte to several bytes and may be followed by addr ess bytes, data bytes, dummy bytes (dont care), and in some cases, a combination. instructions are completed with the rising edge of edge /cs. clock relative timing diagrams for each instruction are included in figures 5 through 57. all read instructions can be completed after any clocked bit. however, all instructions that write, program or erase must complete on a byte boundary (/cs driven high after a full 8 - bits have been clocked) otherwise the instruction will be ignored. this feature further protects the device from inadvertent writes. additionally, while the memory is being programmed or erased, or when the status register is being written, all instructions except for read status register will be ignored until the program or erase cycle has completed . 8.1 device id and instruction set tables manufacturer and device identification manufacturer id (mf7 - mf0) winbond serial flash ef h device id (id7 - id0) (id15 - id0) instruction abh, 90h, 92h, 94h 9fh w25q32jv 15h 4016h
w25q32 jv - 21 - instruction set table 1 (standard spi instructions) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 number of clock (1 - 1 - 1) 8 8 8 8 8 8 8 write enable 06h volatile sr write enable 50h write disable 04h release power - down / id abh dummy dummy dummy (id7 - id0) (2) manufacturer/device id 90h dummy dummy 00h (mf7 - mf0) (id7 - id0) jedec id 9fh (mf7 - mf0) (id15 - id8) (id7 - id0) read unique id 4bh dummy dummy dummy dummy ( uid63 - 0 ) read data 03h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) fast read 0bh a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) page program 02h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) sector erase (4kb) 20h a23 - a16 a15 - a8 a7 - a0 block erase (32kb) 52h a23 - a16 a15 - a8 a7 - a0 block erase (64kb) d8h a23 - a16 a15 - a8 a7 - a0 chip erase c7h /60h read status register - 1 05h (s7 - s0) (2) write status register - 1 (4) 01h (s7 - s0) (4) read status register - 2 35h (s15 - s8) (2) write status register - 2 31h (s15 - s8) read status register - 3 15h (s23 - s16) (2) write status register - 3 11h (s23 - s16) read sfdp register 5ah a23 - a16 a15 - a8 a7 C a0 dummy (d7 - 0) erase security register (5) 44h a23 - a16 a15 - a8 a7 - a0 program security register (5) 42h a23 - a16 a15 - a8 a7 - a0 d7 - d0 d7 - d0 (3) read security register (5) 48h a23 - a16 a15 - a8 a7 - a0 dummy (d7 - d0) global block lock 7eh global block unlock 98h read block lock 3dh a23 - a16 a15 - a8 a7 - a0 (l7 - l0) individual block lock 36h a23 - a16 a15 - a8 a7 - a0 individual block unlock 39h a23 - a16 a15 - a8 a7 - a0 erase / program suspend 75h erase / program resume 7ah power - down b9h enable reset 66h reset device 99h
w25q32 jv publication release date: august 30 , 2016 - 22 - revision c instruction set table 2 (dual/quad spi instructions) (1) data input output byte 1 byte 2 byte 3 byte 4 byte 5 byte 6 byte 7 byte 8 byte 9 number of clock (1 - 1 - 2) 8 8 8 8 4 4 4 4 4 fast read dual output 3bh a23 - a16 a15 - a8 a7 - a0 dummy dummy (d7 - d0 ) (7 ) number of clock (1 - 2 - 2) 8 4 4 4 4 4 4 4 4 fast read dual i/o bbh a23 - a16 (6 ) a15 - a8 (6 ) a7 - a0 (6 ) dummy (11) (d7 - d0 ) (7 ) mftr./device id dual i/o 92h a23 - a16 (6 ) a15 - a8 (6 ) 00 (6 ) dummy (11) (mf7 - mf0) (id7 - id0) (7 ) number of clock ( 1 - 1 - 4) 8 8 8 8 2 2 2 2 2 quad input page program 32h a23 - a16 a15 - a8 a7 - a0 (d7 - d0) ( 9 ) (d7 - d0) ( 3 ) fast read quad output 6bh a23 - a16 a15 - a8 a7 - a0 dummy dummy dummy dummy (d7 - d0) ( 10 ) number of clock (1 - 4 - 4 ) 8 2 (8 ) 2 (8 ) 2 (8 ) 2 2 2 2 2 mftr./device id quad i/o 94h a23 - a16 a15 - a8 00 dummy (11) dummy dummy (mf7 - mf0) (id7 - id0) fast read quad i/o ebh a23 - a16 a15 - a8 a7 - a0 dummy (11) dummy dummy (d7 - d0) set burst with wrap 77h dummy dummy dummy w8 - w0 notes: 1. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ( ) indicate data output from the device on either 1, 2 or 4 io pins. 2. the status register contents and device id will repeat continuously until /cs terminates the instruction. 3. at least one byte of data inpu t is required for page program, quad page program and program security registers, up to 256 bytes of data input. if more than 256 bytes of data are sent to the device, the addressing will wrap to the beginning of the page and overwrite previously sent data . 4. write status register - 1 (01h) can also be used to program status register - 1&2, see section 8.2.5. 5. security register address: security register 1: a23 - 16 = 00h; a15 - 8 = 10h; a7 - 0 = byte address security register 2: a23 - 16 = 00h; a15 - 8 = 20h; a7 - 0 = byte address security register 3: a23 - 16 = 00h; a15 - 8 = 30h; a7 - 0 = byte address 6. dual spi address input format: io0 = a22, a20, a18, a16, a14, a12, a10, a8 a6, a4, a2, a0, m6, m4, m2, m0 io1 = a23, a21, a19, a17, a15, a13, a11, a9 a7, a5, a3, a1, m7, m5, m3, m1 7. dual spi data output format: io0 = (d6, d4, d2, d0) io1 = (d7, d5, d3, d1) 8. quad spi address input format: set burst with wrap input format: io0 = a20, a16, a12, a8, a4, a0, m4, m0 io0 = x, x, x, x, x, x, w4, x io1 = a21, a17, a13, a9, a5, a1, m5, m1 io1 = x, x, x, x, x, x, w5, x io2 = a22, a18, a14, a10, a6, a2, m6, m2 io2 = x, x, x, x, x, x, w6, x io3 = a23, a19, a15, a11, a7, a3, m7, m3 io3 = x, x, x, x, x, x, x, x 9. quad spi data input/output format: io0 = (d4, d0, ..) io1 = (d5, d1, ..) io2 = (d6, d2, ..) io3 = (d7, d3, ..) 10. fast read quad i/o data output format: io0 = (x, x, x, x, d4, d0, d4, d0) io1 = (x, x, x, x, d5, d1, d5, d1) io2 = (x, x, x, x, d6, d2, d6, d2) io3 = (x, x, x, x, d7, d3, d7, d 3) 11. the first dummy is m7 - m0 should be set to f x h
w25q32 jv - 23 - 8.2 instruction descriptions write enable (06h) the write enable instruction (figure 5) sets the write enable latch (wel) bit in the status register to a 1. the wel bit must be set prior to every page program, quad page program, sector erase, block erase, chip erase, write status register and erase/prog ram security registers instruction. the write enable instruction is entered by driving /cs low, shifting the instruction code 06h into the data input (di) pin on the rising edge of clk, and then driving /cs high. figure 5. write enable instruction write enable for volatile status register (50h) the non - volatile status register bits described in section 7.1 can also be written to as volatile bits. this gives more flexibility to change the system configuration and memory protection schemes quickly wit hout waiting for the typical non - volatile bit write cycles or affecting the endurance of the status register non - volatile bits. to write the volatile values into the status register bits, the write enable for volatile status register (50h) instruction must be issued prior to a write status register (01h) instruction. write enable for volatile status register instruction (figure 6) will not set the write enable latch (wel) bit, it is only valid for the write status register instruction to change the volatile status register bit values. figure 6. write enable for volatile status register instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (06h) high impedance /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (50h) high impedance
w25q32 jv publication release date: august 30 , 2016 - 24 - revision c write disable (04h) the write disable instruction (figure 7) resets the write enable latch (wel) bit in the status register to a 0. the write disable instruction is entered by driving /cs low, shifting the instruction code 04h into the di pin and then driving /cs high. note that the wel bit is automatically reset after power - up and upon completion of the write status register, erase/program security r egisters, page program, quad page program, sector erase, block erase, chip erase and reset instructions. figure 7. write disable instruction read status register - 1 (05h), status register - 2 ( 3 5h) & status register - 3 (15h) the read status register instructions allow the 8 - bit status registers to be read. the instruction is entered by driving /cs low and shifting the instruction code 05h for status register - 1, 35h for status register - 2 or 15h for status register - 3 into the di pin on the rising edge of clk. the status register bits are then shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 8. refer to section 7.1 for status register descriptions. the read status register instruction may be used at any time, even while a program, erase or write status register cycle is in progress. this allows the busy status bit to be checked to determine when the cycle is complete and if the device can accept another instruction . the status register can be read continuously, as shown in figure 8. the instruction is completed by driving /cs high. figure 8. read status register instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 mode 0 mode 3 instruction (04h) high impedance / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 5 h / 3 5 h / 1 5 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 s t a t u s r e g i s t e r - 1 / 2 / 3 o u t s t a t u s r e g i s t e r - 1 / 2 / 3 o u t * * = m s b *
w25q32 jv - 25 - write status register - 1 (01h), status register - 2 ( 3 1h) & status register - 3 (11h) the write status register instruction allows the status registers to be written. the writable status register bits include: sec, tb, bp[2:0] in status register - 1; cmp, lb[3:1], qe, srl in status register - 2; drv1, drv0, wps in status register - 3. all other statu s register bit locations are read - only and will not be affected by the write status register instruction. lb[3:1] are non - volatile otp bits, once it is set to 1, it cannot be cleared to 0. to write non - volatile status register bits, a standard write enabl e (06h) instruction must previously have been executed for the device to accept the write status register instruction (status register bit wel must equal 1). once write enabled, the instruction is entered by driving /cs low, sending the instruction code 0 1h/31h/11h, and then writing the status register data byte as illustrated in figure 9a . to write volatile status register bits, a write enable for volatile status register (50h) instruction must have been executed prior to the write status register instru ction (status register bit wel remains 0). however, srl and lb[3:1] cannot be changed from 1 to 0 because of the otp protection for these bits. upon power off or the execution of a software/hardware reset, the volatile status register bit values will b e lost, and the non - volatile status register bit values will be restored. during non - volatile status register write operation (06h combined with 01h/31h/11h), after /cs is driven high, the self - timed write status register cycle will commence for a time dur ation of t w (see ac characteristics). while the write status register cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the write status register cycle and a 0 w hen the cycle is finished and ready to accept other instructions again. after the write status register cycle has finished, the write enable latch (wel) bit in the status register will be cleared to 0. during volatile status register write operation (50h c ombined with 01h/31h/11h), after /cs is driven high, the status register bits will be refreshed to the new values within the time period of t shsl2 (see ac characteristics). busy bit will remain 0 during the status register bit refresh period. refer to sect ion 7.1 for status register descriptions. figure 9a. write status register - 1/2/3 instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 0 1 h / 3 1 h / 1 1 h ) h i g h i m p e d a n c e 8 9 1 0 1 1 1 2 1 3 1 4 1 5 7 6 5 4 3 2 1 0 r e g i s t e r - 1 / 2 / 3 i n m o d e 0 m o d e 3 * = m s b *
w25q32 jv publication release date: august 30 , 2016 - 26 - revision c the w25q32 jv is also backward compatible to winbonds previous generations of serial flash memories, in which the status register - 1&2 can be written using a single write status register - 1 (01h) command. to complete the write status register - 1&2 instruction, the /cs pin must be driven high after the sixteenth bit of data that is clocked in as shown in figure 9 b . if /cs is driven high after the eighth clock, the write status register - 1 (01h) instruction will only program the status register - 1, the status register - 2 will not be affected (previous generations will clear cmp and qe bits). figure 9 b . write status register - 1/2 instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (01h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 status register 1 in status register 2 in mode 0 mode 3 * * = msb *
w25q32 jv - 27 - read data (03 h) the read data instruction allows one or more data bytes to be sequentially read from the memory. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 03h followed by a 24 - bit address (a23 - a0) into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the a ddress is automatically incremented to the next higher address after each byte of data is shifted out allowing for a continuous stream of data. this means that the entire memory can be accessed with a single instruction as long as the clock continues. the instruction is completed by driving /cs high. the read data instruction sequence is shown in figure 14. if a read data instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effe cts on the current cycle. the read data instruction allows clock rates from d.c. to a maximum of f r (see ac electrical characteristics). figure 14. read data instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (03h) high impedance 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 7 6 5 4 3 2 1 0 7 24-bit address 23 22 21 3 2 1 0 data out 1 * * = msb *
w25q32 jv publication release date: august 30 , 2016 - 28 - revision c fast read (0bh) the fast read instruction is similar to the read data instruction except that it can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 16. the dummy clocks allow the devices inter nal circuits additional time for setting up the initial address. during the dummy clocks the data value on the do pin is a dont care. figure 16. fast read instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (0bh) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy clocks high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 43 31 0 = msb *
w25q32 jv - 29 - fast read dual output (3bh) the fast read dual output (3bh) instruction is sim ilar to the standard fast read (0bh) instruction except that data is output on two pins; io 0 and io 1 . this allows data to be transferred at twice the rate of standard spi devices. the fast read dual output instruction is ideal for quickly downloading code from flash to ram upon power - up or for applications that cache code - segments to ram for execution. similar to the fast read instruction, the fast read dual output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 18. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input da ta during the dummy clocks is dont care. however, the io 0 pin should be high - impedance prior to the falling edge of the first data out clock. figure 18. fast read dual output instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (3bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 6 4 2 0 24-bit address 23 22 21 3 2 1 0 * * 31 31 /cs clk di (io 0 ) do (io 1 ) dummy clocks 0 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 7 5 3 1 high impedance 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 io 0 switches from input to output 6 7 data out 1 * data out 2 * data out 3 * data out 4 = msb *
w25q32 jv publication release date: august 30 , 2016 - 30 - revision c fast read quad output (6bh) the fast read quad output (6bh) instruction is similar to the fast read dual output (3bh) instruction except that data is output on four pins, io 0 , io 1 , io 2 , and io 3 . the quad enable (qe) bit in status register - 2 must be set to 1 before the device will accept the fast read quad output i nstruction . the fast read quad output instruction allows data to be transferred at four times the rate of standard spi devices. the fast read quad output instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding eight dummy clocks after the 24 - bit address as shown in figure 20. the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont c are. however, the io pins should be high - impedance prior to the falling edge of the first data out clock. figure 20. fast read quad output instruction /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (6bh) high impedance 8 9 10 28 29 30 32 33 34 35 36 37 38 39 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk dummy clocks 0 40 41 42 43 44 45 46 47 5 1 high impedance 4 5 byte 1 high impedance high impedance 6 2 7 3 high impedance 6 7 high impedance 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 4 io 0 switches from input to output io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 = msb *
w25q32 jv - 31 - f ast read dual i/o (bbh) the fast read dual i/o (bbh) instruction allows for improved random access while maintaining two io pins, io 0 and io 1 . it is similar to the fast read dual output (3bh) instruction but with the capability to input the address bits (a23 - 0) two bits per clock. this reduced instruction overhead may allow for code execution (xi p) directly from the d ua l spi in some applications. similar to the fast read dual output (3bh) instruction, the fast read dual i/o instruction can operate at the highest possible frequency of f r (see ac electrical characteristics). this is accomplished by adding four dummy clocks after the 24 - bit address as shown in figure 22 . the dummy clocks allow the device's internal circuits additional time for setting up the initial address. the input data during the dummy clocks is dont care. however, the io 0 p in should be high - impedance prior to the falling edge of the first data out clock. figure 22. fast read dual i/ o instruction ( m7 - m0 should be set to f x h ) /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (bbh) 8 9 10 12 13 14 24 25 26 27 28 29 30 31 6 4 2 0 * * 23 /cs clk di (io 0 ) do (io 1 ) 0 32 33 34 35 36 37 38 39 7 5 3 1 * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 * * ios switch from input to output 6 7 22 20 18 16 23 21 19 17 14 12 10 8 15 13 11 9 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 11 15 16 17 18 20 21 22 19 23 1 a23-16 a15-8 a7-0 m7-0 byte 1 byte 2 byte 3 byte 4 = msb * *
w25q32 jv publication release date: august 30 , 2016 - 32 - revision c fast read quad i/o (ebh) the fast read quad i/o (ebh) instruction is similar to the fast read dual i/o (bbh) instruction except that address and data bits are input and output through four pins io 0 , io 1 , io 2 and io 3 and four dummy clocks are required in spi mode prior to the data output. the quad i/o dramatically reduces instruction overhead a llowing faster random access for code execution (xip) directly from the quad spi. the quad enable bit (qe) of status register - 2 must be set to enable the fast read quad i/o instruction . figure 24. fast read quad i/ o instruction ( m7 - m0 should be set to f x h ) fast read quad i/o with 8/16/32/64 - byte wrap around the fast read quad i/o instruction can also be used to access a specific portion within a page by issuing a set burst with wrap (77h) command prior to ebh. the set bur st with wrap (77h) command can either enable or disable the wrap around feature for the following ebh commands. when wrap around is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64 - byte section of a 256 - byte page. the outpu t data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64 - byte section, the output will wrap around to the beginning boundary automatically until /cs is pulled high to terminate the command. t he burst with wrap feature allows applications that use cache to quickly fetch a critical address and then fill the cache afterwards within a fixed length (8/16/32/64 - byte) of data without issuing multiple read commands. the set burst with wrap instruct ion allows three wrap bits, w6 - 4 to be set. the w4 bit is used to enable or disable the wrap around operation while w6 - 5 are used to specify the length of the wrap around section within a page. refer to section 8.2.37 for detail descriptions. m7-0 /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 20 16 12 8 21 17 22 18 23 19 13 9 14 10 15 11 a23-16 6 7 8 9 4 0 5 1 6 2 7 3 a15-8 a7-0 byte 1 byte 2 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 10 11 12 13 14 4 5 6 7 ios switch from input to output byte 3 15 16 17 18 19 20 21 22 23 dummy dummy instruction (ebh)
w25q32 jv - 33 - set bu rst with wrap (77h) t he set burst with wrap (77h) instruction is used in conjunction with fast read quad i/o instruction to access a fixed length of 8/16/32/64 - byte section within a 256 - byte page. certain applications can benefit from this feature and im prove the overall system code execution performance. similar to a quad i/o instruction, the set burst with wrap instruction is initiated by driving the /cs pin low and then shifting the instruction code 77h followed by 24 dummy bits and 8 wrap bits, w7 - 0. the instruction sequence is shown in figure 28. wrap bit w7 and the lower nibble w3 - 0 are not used. w6, w5 w4 = 0 w4 =1 (default) wrap around wrap length wrap around wrap length 0 0 yes 8 - byte no n/a 0 1 yes 16 - byte no n/a 1 0 yes 32 - byte no n/a 1 1 yes 64 - byte no n/a once w6 - 4 is set by a set burst with wrap instruction, all the following fast read quad i/o instruction will use the w6 - 4 setting to access the 8/16/32/64 - byte section within any page. to exit the wrap around function and return to normal read operation, another set burst with wrap instruction should be issued to set w4 = 1. the default value of w4 upon power on or after a software/hardware reset is 1. figure 28. set burst with wrap instruction wrap bit /cs clk mode 0 mode 3 0 1 io 0 io 1 io 2 io 3 2 3 4 5 x x x x x x x x don't care 6 7 8 9 don't care don't care 10 11 12 13 14 15 instruction (77h) mode 0 mode 3 x x x x x x x x x x x x x x x x w4 x w5 x w6 x x x
w25q32 jv publication release date: august 30 , 2016 - 34 - revision c page program (02h) th e page program instruction allows from one byte to 256 bytes (a page) of data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the page program instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 02h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. the page program instruction sequence is shown in figure 29. if an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits) should be set to 0. if the las t address byte is not zero, and the number of clocks exceeds the remaining page length, the addressing will wrap to the beginning of the page. in some cases, less than 256 bytes (a partial page) can be programmed without having any effect on other bytes wi thin the same page. one condition to perform a partial page program is that the number of clocks cannot exceed the remaining page length. if more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page and overwrite prev iously sent data. as with the write and erase instructions, the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the page program instruction will not be executed. after /cs is driven high, the self - ti med page program instruction will commence for a time duration of tpp (see ac characteristics). while the page program cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the page program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the page program cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the page program instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 29. page program instruction /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (02h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32 jv - 35 - quad input page program ( 3 2h) the quad page program instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: io 0 , io 1 , io 2 , and io 3 . the quad page program can improve performance for prom programmer and applications tha t have slow clock speeds <5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock - in the data. to use quad page program th e quad enable (qe) bit in status register - 2 must be set to 1. a write enable instruction must be executed before the device will accept the quad page program instruction (status register - 1, wel=1). the instruction is initiated by driving the /cs pin low th en shifting the instruction code 32h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the io pins. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad page program are identical to standard page program. the quad page program instruction sequence is shown in figure 30. figure 30. quad input page program instruction /cs clk mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (32h) 8 9 10 28 29 30 32 33 34 35 36 37 4 0 24-bit address 23 22 21 3 2 1 0 * 31 31 /cs clk 5 1 byte 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 byte 2 byte 3 byte 256 0 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 4 0 5 1 6 2 7 3 536 537 538 539 540 541 542 543 mode 0 mode 3 byte 253 byte 254 byte 255 io 0 io 1 io 2 io 3 io 0 io 1 io 2 io 3 * * * * * * * = msb *
w25q32 jv publication release date: august 30 , 2016 - 36 - revision c sector erase (20h) the sector erase instruction sets all memory within a specified sector (4k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the sector erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 20h followed a 24 - bit sector address (a23 - a0). the sector erase instruction sequence is shown in figure 31 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not d one the sector erase instruction will not be executed. after /cs is driven high, the self - timed sector erase instruction will commence for a time duration of t se (see ac characteristics). while the sector erase cycle is in progress, the read status registe r instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the sector erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the sector erase cyc le has finished the write enable latch (wel) bit in the status register is cleared to 0. the sector erase instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual bloc k/sector locks. figure 31. sector erase instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (20h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32 jv - 37 - 32kb block erase (52h) the block erase instruction sets all memory within a specified block (32k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code 52h followed a 24 - bit block address (a23 - a0). the block erase instruction seq uence is shown in figure 32. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be 1 (see ac characteristics). while the block erase cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not b e executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual block/sector locks. figure 32. 32kb block erase instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (52h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32 jv publication release date: august 30 , 2016 - 38 - revision c 64kb block erase (d8h) the block erase instruction sets all memor y within a specified block (64k - bytes) to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the block erase instruction (status register bit wel must equal 1). the instruction is initiated by drivin g the /cs pin low and shifting the instruction code d8h followed a 24 - bit block address (a23 - a0). the block erase instruction sequence is shown in figure 33. the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the block erase instruction will not be executed. after /cs is driven high, the self - timed block erase instruction will commence for a time duration of t be (see ac characteristics). while the block erase cycle is in progress, the read status re gister instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the block erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. after the block erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the block erase instruction will not be executed if the addressed page is protected by the block protect (cmp, sec, tb, bp2, bp1, and bp0) bits or the individual bl ock/sector locks. figure 33. 64kb block erase instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (d8h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32 jv - 39 - chip erase (c7h / 60h ) the chip erase instruction sets all memory within the device to the erased state of all 1s (ffh). a write enable instruction must be executed before the device will accept the chip erase instruction (status register bit wel must equal 1). the instruction is initiated by driving the /cs pin low and shifting the instruction code c7h or 60h . the chip erase instruction sequence is shown in figure 34. the /cs pin must be driven high after the eighth bit has been latched. if this is not done the chip erase instruction will not be executed. after /cs is driven high, the self - timed chip erase instruction will commence for a time duration of t ce (see ac characteristics). wh ile the chip erase cycle is in progress, the read status register instruction may still be accessed to check the status of the busy bit. the busy bit is a 1 during the chip erase cycle and becomes a 0 when finished and the device is ready to accept other i nstructions again. after the chip erase cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the chip erase instruction will not be executed if any memory region is protected by the block protect (cmp, sec, tb, bp2, b p1, and bp0) bits or the individual block/sector locks. figure 3 4. chip erase instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (c7h/60h) high impedance mode 0 mode 3
w25q32 jv publication release date: august 30 , 2016 - 40 - revision c erase / program suspend (75h) the erase/program suspend instruction 75h, allows the system to interrupt a sector or block erase operation or a page program operation and then read from or program/erase data to, any other sectors or blocks. the erase/program suspend instruction sequence is shown in figure 35. the write status register instruction (01h) and erase instructions (20h, 52h, d8h, c7h , 60h, 44h) are not allowed during erase suspend. erase suspend is valid only during the sector or block erase operation. if written during the chip erase operation, the erase suspend instruction is ignored. the write status register instruction (01h) and program instructions (02h, 32h, 42h) are not allowed during program suspend. program suspend is valid only during the page program or quad page program operation. the erase/program suspend instruction 75h will be accepted by the device only if the sus bi t in the status register equals to 0 and the busy bit equals to 1 while a sector or block erase or a page program operation is on - going. if the sus bit equals to 1 or the busy bit equals to 0, the suspend instruction will be ignored by the device. a maximu m of time of t sus (see ac characteristics) is required to suspend the erase or program operation. the busy bit in the status register will be cleared from 1 to 0 within t sus and the sus bit in the status register will be set from 0 to 1 immediately aft er erase/program suspend. for a previously resumed erase/program operation, it is also required that the suspend instruction 75h is not issued earlier than a minimum of time of t sus following the preceding resume instruction 7ah. unexpected power off during the erase/program suspend state will reset the device and release the suspend state. sus bit in the status register will also reset to 0. the data within the page, sector or block that was being suspended may become corrupted. it is recommended for the user to implement system design techniques against the accidental power interruption and preserve data integrity during erase/program suspend state. figure 35 . erase/program suspend instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (75h) high impedance mode 0 mode 3 tsus accept instructions
w25q32 jv - 41 - erase / program resume (7ah) the erase/program resume instruction 7ah must be written to resume the sector or block erase operation or the page program operation after an erase/program suspend. the resume instruction 7ah will be accepted by the device only if the sus bit in the status register equa ls to 1 and the busy bit equals to 0. after issued the sus bit will be cleared from 1 to 0 immediately, the busy bit will be set from 0 to 1 within 200ns and the sector or block will complete the erase operation or the page will complete the program operat ion. if the sus bit equals to 0 or the busy bit equals to 1, the resume instruction 7ah will be ignored by the device. the erase/program resume instruction sequence is shown in figure 36. resume instruction is ignored if the previous erase/program suspen d operation was interrupted by unexpected power off. it is also required that a subsequent erase/program suspend instruction not to be issued within a minimum of time of t sus following a previous resume instruction. figure 36 . erase/program resume instruction /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (7ah) mode 0 mode 3 resume previously suspended program or erase
w25q32 jv publication release date: august 30 , 2016 - 42 - revision c power - down (b9h) although the standby current during normal operation is relatively low, standby current can be further reduced with the power - down instruction. the lower power consumption makes the power - down instruction especially useful for battery powered applications (see icc1 and icc2 in ac characteristics). the instruction is initiated by driving the /cs pin low and shifting the instruction code b9h as shown in figure 37 . the /cs pin must be driven high after the eighth bit has bee n latched. if this is not done the power - down instruction will not be executed. after /cs is driven high, the power - down state will entered within the time duration of t dp (see ac characteristics). while in the power - down state only the release power - down / device id (abh) instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but on e instruction makes the power down state a useful condition for securing maximum write protection. the device always powers - up in the normal operation with the standby current of icc1. figure 37 . deep power - down instruction /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (b9h) mode 0 mode 3 tdp power-down current stand-by current
w25q32 jv - 43 - release power - down / device id (abh) the release from power - down / device id instruction is a multi - purpose instruction. it can be used to release the device from the power - down state , or obtain the devices electronic identification (id) number. to release the device from th e power - down state, the instruction is issued by driving the /cs pin low, shifting the instruction code abh and driving /cs high as shown in figure 38a . release from power - down will take the time duration of t res 1 (see ac characteristics) before the devi ce will resume normal operation and other instructions are accepted. the /cs pin must remain high during the t res 1 time duration. when used only to obtain the device id while not in the power - down state, the instruction is initiated by driving the /cs pin low and shifting the instruction code abh followed by 3 - dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first. the device id value for the w25q32 jv is listed in manufacturer and device ident ification table. the device id can be read continuously. the instruction is completed by driving /cs high. when used to release the device from the power - down state and obtain the device id, the instruction is the same as previously described, and shown i n figure 38 b , except that after /cs is driven high it must remain high for a time duration of t res 2 (see ac characteristics). after this time duration the device will resume normal operation and other instructions will be accepted. if the release from powe r - down / device id instruction is issued while an erase, program or write cycle is in process (when busy equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 38a . release power - down instruction figure 38 b . release power - down / device id instruction /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) mode 0 mode 3 tres1 power-down current stand-by current tres2 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (abh) high impedance 8 9 29 30 31 3 dummy bytes 23 22 2 1 0 * mode 0 mode 3 7 6 5 4 3 2 1 0 * 32 33 34 35 36 37 38 device id power-down current stand-by current = msb *
w25q32 jv publication release date: august 30 , 2016 - 44 - revision c read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power - down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power - down / device id instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 90h followed by a 2 4 - bit address (a23 - a0) of 000000h. after which, the manufacturer id for winbond (efh) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 39 . the device id values for the w25q32 jv are listed in manufacturer and device identification table. the instruction is completed by driving /cs high. figure 39 . read manufacturer / device id instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (90h) high impedance 8 9 10 28 29 30 31 address (000000h) 23 22 21 3 2 1 0 device id * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 manufacturer id (efh) 40 41 42 44 45 46 7 6 5 4 3 2 1 0 * 43 31 0 mode 0 mode 3 = msb *
w25q32 jv - 45 - read manufacturer / device id dual i/o (92h) the read manufacturer / device id dual i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the jedec assigned manufacturer id and the specific device id at 2x speed. the read manufacturer / device id dual i/o instruction is similar to the fast read dual i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruction code 92h followed by a 24 - bit address (a23 - a0) of 000000h, but with the capability to input the address bits two bits per clock . after which, the m anufacturer id for winbond (efh) and the device id are shifted out 2 bits per clock on the falling edge of clk with most significant bits (msb) first as shown in figure 40 . the device id values for the w25q32 jv are listed in manufacturer and device identif ication table. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 40 . read manufacturer / device id dual i/o instruction note: the bits m(7 - 0) must be s et to fxh to be compatible with fast read dual i/o instruction. /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (92h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 7 5 3 1 * * 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 23 * * a23-16 a15-8 a7-0 (00h) m7-0 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 0 mode 0 mode 3 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 1 6 4 2 0 7 5 3 6 4 2 1 0 1 mfr id device id mfr id (repeat) device id (repeat) ios switch from input to output * * * * = msb *
w25q32 jv publication release date: august 30 , 2016 - 46 - revision c read manufacturer / device id quad i/o (94h) the read manufacturer / device id quad i/o instruction is an alternative to the read manufacturer / device id instruction that provides both the j edec assigned manufacturer id and the specific device id at 4x speed. the read manufacturer / device id quad i/o instruction is similar to the fast read quad i/o instruction. the instruction is initiated by driving the /cs pin low and shifting the instruc tion code 94h followed by a four clock dummy cycles and then a 24 - bit address (a23 - a0) of 000000h, but with the capability to input the address bits four bits per clock . after which, the manufacturer id for winbond (efh) and the device id are shifted out four bits per clock on the falling edge of clk with most significant bit (msb) first as shown in figure 41 . the device id values for the w25q32 jv are listed in manufacturer and device identification table. the manufacturer and device ids can be read conti nuously, alternating from one to the other. the instruction is completed by driving /cs high. figure 41 . read manufacturer / device id quad i/o instruction note: the continuous read mode bits m(7 - 0) must be set to fxh to be compatible with fast read quad i/o instruction. mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (94h) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 5 1 4 0 23 mode 0 mode 3 ios switch from input to output high impedance 7 3 6 2 /cs clk io 0 io 1 io 2 io 3 high impedance a23-16 a15-8 a7-0 (00h) m7-0 mfr id device id dummy dummy /cs clk io 0 io 1 io 2 io 3 23 0 1 2 3 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 5 1 4 0 7 3 6 2 24 25 26 27 28 29 30 mfr id (repeat) device id (repeat) mfr id (repeat) device id (repeat)
w25q32 jv - 47 - read unique id number (4bh) the read unique id number instruction accesses a factory - set read - only 64 - bit number that is unique to each w25q32 jv device. the id number can be used in conjunction with u ser software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the /cs pin low and shifting the instruction code 4bh followed by a four bytes of dummy clocks. after which, the 64 - bit id is shif ted out on the falling edge of clk as shown in figure 42 . figure 42 . read unique id number instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (4bh) high impedance 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 /cs clk di (io 0 ) do (io 1 ) 24 25 26 27 28 29 30 31 32 33 34 36 37 38 35 23 mode 0 mode 3 * dummy byte 1 dummy byte 2 39 40 41 42 dummy byte 3 dummy byte 4 63 62 61 2 1 0 64-bit unique serial number 100 101 102 high impedance = msb *
w25q32 jv publication release date: august 30 , 2016 - 48 - revision c read jedec id (9fh) for compatibility reasons, the w25q32 jv provides several instructions to electronically determine the identity of the device. the read jedec id instruction is compatible with the jedec standard for spi compatible serial memories that was adopted in 2003. the instruction is initiated by driving the /cs pin low and shifting the instruction code 9fh. the jedec assigned manufacturer id byte for winbond (efh) and two device id bytes, memory type (id15 - id8) and capacity (id7 - id0) are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 43 . for memory type and capacity values refer to manufacturer and device identification table. figure 43 . read jedec id instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (9fh) high impedance 8 9 10 12 13 14 15 capacity id7-0 /cs clk di (io 0 ) do (io 1 ) 16 17 18 19 20 21 22 23 manufacturer id (efh) 24 25 26 28 29 30 7 6 5 4 3 2 1 0 * 27 15 mode 0 mode 3 11 7 6 5 4 3 2 1 0 * memory type id15-8 = msb *
w25q32 jv - 49 - read sfdp register (5ah) the w25q32jv features a 256 - byte serial flash discoverable parameter (sfdp) register that contains information about device configurations, available instructions and other features . the sfdp parameters are stored in one or more parameter identification (pid) tables. currently only one pid table is specified, but more may be added in the future. the read sfdp register instruction is com patible with the sfdp standard initially established in 2010 for pc and other applications, as well as the jedec standard jesd216 - seria ls that is published in 2011 . most winbond spiflash memories shipped after june 2011 (date code 1124 and beyond) support the sfdp feature as specified in the applicable datasheet. the read sfdp instruction is initiated by driving the /cs pin low and shift ing the instruction code 5ah followed by a 24 - bit address (a23 - a0) (1) into the di pin. eight dummy clocks are also required before the sfdp register contents are shifted out on the falling edge of the 40 th clk with most significant bit (msb) first as s hown in figure 3 4 . for sfdp register values and descriptions, please refer to the winbond application note for sfdp definition t able. note 1: a23 - a8 = 0; a7 - a0 are used to define the starting byte address for the 256 - byte sfdp register. figure 3 4 . read sfdp register instruction sequence diagram /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (5ah) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32 jv publication release date: august 30 , 2016 - 50 - revision c erase security registers (44h) the w25q32jv offers three 256 - byte security registers which can be erased and programmed individually. these registers may be used by the system manufacturers to store security and other important information separately from the main memory array. the erase security r egister instruction is similar to the sector erase instruction. a write enable instruction must be executed before the device will accept the erase security register instruction (status register bit wel must equal 1). the instruction is initiated by drivin g the /cs pin low and shifting the instruction code 44h followed by a 24 - bit address (a23 - a0) to erase one of the three security registers. address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 dont care security register #2 00h 0 0 1 0 0 0 0 0 dont care security register #3 00h 0 0 1 1 0 0 0 0 dont care the erase security register instruction sequence is shown in figure 45 . the /cs pin must be driven high after the eighth bit of the last byte has been latched. if this is not done the instruction will not be executed. after /cs is driven high, the self - timed erase security register operation will commence for a time duration of t se (see ac characteristics). while the erase security register cycle is in progress, the read status register instruction may still be accessed for checking the status of the busy bit. the busy bit is a 1 during the erase cycle and becomes a 0 when th e cycle is finished and the device is ready to accept other instructions again. after the erase security register cycle has finished the write enable latch (wel) bit in the status register is cleared to 0. the security register lock bits (lb3 - 1) in the sta tus register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register will be permanently locked, erase security register instruction to that register will be ignored (refer to section 7.1. 9 for detail descriptions). figure 45 . erase security registers instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (44h) high impedance 8 9 29 30 31 24-bit address 23 22 2 1 0 * mode 0 mode 3 = msb *
w25q32 jv - 51 - program security registers (42h) the program security register instruction is similar to the page program instruction. it allows from one byte to 256 bytes of security register data to be programmed at previously erased (ffh) memory locations. a write enable instruction must be executed before the device will accept the program security register instruction (status register bit wel= 1). the instruction is initiated by driving the /cs pin low then shifting the instruction code 42h followed by a 24 - bit address (a23 - a0) and at least one data byte, into the di pin. the /cs pin must be held low for the entire length of the instruction while data is being sent to the device. address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address the program security register instruction sequence is shown in figure 46 . the security register lock bits (lb3 - 1) in the status register - 2 can be used to otp protect the security registers. once a lock bit is set to 1, the corresponding security register w ill be permanently locked, program security register instruction to that register will be ignored (see 7.1. 9 for detail descriptions). figure 46 . program security registers instruction /cs clk di (io 0 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (42h) 8 9 10 28 29 30 39 24-bit address 23 22 21 3 2 1 * /cs clk di (io 0 ) 40 41 42 43 44 45 46 47 data byte 2 48 49 50 52 53 54 55 2072 7 6 5 4 3 2 1 0 51 39 0 31 0 32 33 34 35 36 37 38 data byte 1 7 6 5 4 3 2 1 * mode 0 mode 3 data byte 3 2073 2074 2075 2076 2077 2078 2079 0 data byte 256 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 * = msb *
w25q32 jv publication release date: august 30 , 2016 - 52 - revision c read security registers (48h) the read security register instruction is similar to the fast read instruction and allows one or more data bytes to be sequentially read from one of the four security registers. the instruction is initiated by driving the /cs pin low and then shifting the instruction code 48h followed by a 24 - bit address (a23 - a0) and eight dummy clocks into the di pin. the code and address bits are latched on the rising edge of the clk pin. after the address is received, the data byte of the addressed memory location wi ll be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first. the byte address is automatically incremented to the next byte address after each byte of data is shifted out. once the byte address reaches the last byte of the register (byte address ffh), it will reset to address 00h, the first byte of the register, and continue to increment. the instruction is completed by driving /cs high. the read security register instruction sequence is shown in figure 47. if a read sec urity register instruction is issued while an erase, program or write cycle is in process (busy=1) the instruction is ignored and will not have any effects on the current cycle. the read security register instruction allows clock rates from d.c. to a maxim um of f r (see ac electrical characteristics). address a23 - 16 a15 - 12 a11 - 8 a7 - 0 security register #1 00h 0 0 0 1 0 0 0 0 byte address security register #2 00h 0 0 1 0 0 0 0 0 byte address security register #3 00h 0 0 1 1 0 0 0 0 byte address figure 47 . read security registers instruction /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (48h) high impedance 8 9 10 28 29 30 31 24-bit address 23 22 21 3 2 1 0 data out 1 * /cs clk di (io 0 ) do (io 1 ) 32 33 34 35 36 37 38 39 dummy byte high impedance 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 7 6 5 4 3 2 1 0 7 data out 2 * 7 6 5 4 3 2 1 0 * 7 6 5 4 3 2 1 0 43 31 0 = msb *
w25q32 jv - 53 - individual block/sector lock (36h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will b e determined by the combination of cmp, sec, tb, bp[2:0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to lock a specific block or sector as illustrated in figure 4d, an individual block/sector lock command must be issued by driving /cs low, shifting the instruction code 36h into the data input (di) pin on the rising edge of clk, followed by a 24 - bit addr ess and then driving /cs high. a write enable instruction must be executed before the device will accept the individual block/sector lock instruction (status register bit wel= 1). figure 5 3 . individual block/sector lock instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 6 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b *
w25q32 jv publication release date: august 30 , 2016 - 54 - revision c individual block/sector unlock (39h) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, t he write protection will be determined by the combination of cmp, sec, tb, bp[2:0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to unlock a specific block or sector as illustrated in figure 4d, an individual block/sector unlock command must be issued by driving /cs low, shifting the instruction code 39h into the data input (di) pin on the rising edge of clk, followed by a 24 - bit address and then driving /cs high. a write enable instruction must be executed before the device will accept the individual block/sector unlock instruction (status register bit wel= 1). figure 5 4 . individual block unlock instru ction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 9 h ) h i g h i m p e d a n c e 8 9 2 9 3 0 3 1 2 4 - b i t a d d r e s s 2 3 2 2 2 1 0 * m o d e 0 m o d e 3 = m s b *
w25q32 jv - 55 - read block/sector lock (3dh) the individual block/sector lock provides an alternative way to protect the memory array from adverse erase/program. in order to use the individual block/sector locks, the wps bit in status register - 3 must be set to 1. if wps=0, the write protection will b e determined by the combination of cmp, sec, tb, bp[2:0] bits in the status registers. the individual block/sector lock bits are volatile bits. the default values after device power up or after a reset are 1, so the entire memory array is being protected. to read out the lock bit value of a specific block or sector as illustrated in figure 4d, a read block/sector lock command must be issued by driving /cs low, shifting the instruction code 3dh into the data input (di) pin on the rising edge of clk, follow ed by a 24 - bit address. the block/sector lock bit value will be shifted out on the do pin at the falling edge of clk with most significant bit (msb) first as shown in figure 5 5 . if the least significant bit (lsb) is 1, the corresponding block/sector is loc ked; if lsb=0, the corresponding block/sector is unlocked, erase/program operation can be performed. figure 5 5 . read block lock instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 i n s t r u c t i o n ( 3 d h ) h i g h i m p e d a n c e 8 9 1 0 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 x x x x x x x 0 2 4 - b i t a d d r e s s 2 3 2 2 2 1 3 2 1 0 l o c k v a l u e o u t * * = m s b * m o d e 0 m o d e 3
w25q32 jv publication release date: august 30 , 2016 - 56 - revision c global block/sector lock (7eh) all block/sector lock bits can be set to 1 by the global block/sector lock ins truction. the command must be issued by driving /cs low, shifting the instruction code 7eh into the data input (di) pin on the rising edge of clk, and then driving /cs high. a write enable instruction must be executed before the device will accept the gl obal block/sector lock instruction (status register bit wel= 1). figure 5 6 . global block lock instruction global block/sector unlock (98h) all block/sector lock bits can be set to 0 by the global block/sector unlock instruction. the command must be issued by driving /cs low, shifting the instruction code 98h into the data input (di) pin on the rising edge of clk, and then driving /cs high. a write enable instruction must be executed before the device will accept the global block/sector unlock instr uction (status register bit wel= 1). figure 5 7 . global block unlock instruction / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 7 e h ) h i g h i m p e d a n c e / c s c l k d i ( i o 0 ) d o ( i o 1 ) m o d e 0 m o d e 3 0 1 2 3 4 5 6 7 m o d e 0 m o d e 3 i n s t r u c t i o n ( 9 8 h ) h i g h i m p e d a n c e
w25q32 jv - 57 - enable reset (66h) and reset device (99h) because of the small package and the limitation on the number of pins, the w25q32 jv provide a software reset instruction instead of a dedicated reset pin. once the reset instruction is accepted, any on - going internal operations will be terminated and the device will return to its default power - on state and lose all the current volatile s ettings, such as volatile status register bits, write enable latch (wel) status, program/erase suspend status, read parameter setting (p7 - p0), continuous read mode bit setting (m7 - m0) and wrap bit setting (w6 - w4). enable reset (66h) and reset (99h) ins tructions can be issued in spi. to avoid accidental reset, both instructions must be issued in sequence. any other commands other than reset (99h) after the enable reset (66h) command will disable the reset enable state. a new sequence of enable res et (66h) and reset (99h) is needed to reset the device. once the reset command is accepted by the device, the device will take approximately trst=30us to reset. during this period, no command will be accepted. data corruption may happen if there is an o n - going or suspended internal erase or program operation when reset command sequence is accepted by the device. it is recommended to check the busy bit and the sus bit in status register before issuing the reset command sequence. figure 5 8 . enable reset and reset instruction sequence mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (99h) mode 0 mode 3 /cs clk di (io 0 ) do (io 1 ) mode 0 mode 3 0 1 2 3 4 5 6 7 instruction (66h) high impedance
w25q32 jv publication release date: august 30 , 2016 - 58 - revision c 9. electrical character istics 9.1 absolute maximum ratings (1) parameters symbol conditions range unit supply voltage vcc C 0.6 to 4.6 v voltage applied to any pin v io relative to ground C 0.6 to vcc+0.4 v transient voltage on any pin v iot <20ns transient relative to ground C 2.0v to vcc+2.0v v storage temperature t stg C 65 to +150 c lead temperature t lead see note (2) c electrostatic discharge voltage v esd human body model (3) C 2000 to +2000 v notes: 1. this device has been designed and tested for the specified operation ranges. proper operation outside of these levels is not guaranteed. exposure to absolute maximum ratings may affect device reliability. exposure beyond absolute maximum ratings may cau se permanent damage. 2. compliant with jedec standard j - std - 20c for small body sn - pb or pb - free (green) assembly and the european directive on restrictions on hazardous substances (rohs) 2002/95/eu. 3. jedec std jesd22 - a114a (c1=100pf, r1=1500 ohms, r2=500 ohms). 9.2 operating ranges parameter symbol conditions spec unit min max supply voltage (1) vcc f r = 133mhz , f r = 50 mhz 3.0 3.6 v f r = 104mhz , f r = 50 mhz 2.7 3.0 v ambient temperature, operating t a industrial C 40 +85 c note: 1. vcc voltage during read can operate across the min and max range but should not exceed 10% of the programming (erase/write) voltage.
w25q32 jv - 59 - 9.3 power - up power - down timing and requirements parameter symbol spec unit min max vcc (min) to /cs low t vsl (1) 20 s time delay before write instruction t puw (1) 5 ms write inhibit threshold voltage v wi (1) 1.0 2.0 v note: 1. these parameters are characterized only. figure 58a. power - up timing and voltage levels figure 58b. power - up, power - down requirement vcc tvsl read instructions allowed device is fully accessible tpuw /cs must track vcc program, erase and write instructions are ignored reset state vcc (max) vcc (min) v wi time vcc time / cs must track vcc during vcc ramp up / down / cs
w25q32 jv publication release date: august 30 , 2016 - 60 - revision c 9.4 dc electrical characteristics - parameter symbol conditions spec unit min typ max input capacitance c in (1) v in = 0v (1) 6 pf output capacitance cout (1) v out = 0v (1) 8 pf input leakage i li 2 a i/o leakage i lo 2 a standby current i cc 1 /cs = vcc, vin = gnd or vcc 10 50 a power - down current i cc 2 /cs = vcc, vin = gnd or vcc 1 15 a current read data / dual /quad 50mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 15 ma current read data / dual /quad 80mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 18 ma current read data / dual output read /quad output read 104 mhz (2) i cc 3 c = 0.1 vcc / 0.9 vcc do = open 20 ma current write status register i cc 4 /cs = vcc 20 25 ma current page program i cc 5 /cs = vcc 20 25 ma current sector/block erase i cc 6 /cs = vcc 20 25 ma current chip erase i cc 7 /cs = vcc 20 25 ma input low voltage v il C 0.5 vcc x 0.3 v input high voltage v ih vcc x 0.7 vcc + 0.4 v output low voltage v ol i ol = 100 a 0.2 v output high voltage v oh i oh = C 100 a vcc C 0.2 v notes: 1. tested on sample basis and specified through design and characterization data. ta = 25 c, vcc = 3.0v. 2. checker board pattern.
w25q32 jv - 61 - 9.5 ac measurement conditions parameter symbol spec unit min max load capacitance c l 30 pf input rise and fall times t r , t f 5 ns input pulse voltages v in 0.1 vcc to 0.9 vcc v input timing reference voltages in 0.3 vcc to 0.7 vcc v output timing reference voltages o ut 0. 5 vcc to 0. 5 vcc v note: 1. output hi - z is defined as the point where data out is no longer driven. figure 59. ac measurement i/o waveform input and output timing reference levels input levels 0.9 vcc 0.1 vcc 0.5 vcc
w25q32 jv publication release date: august 30 , 2016 - 62 - revision c 9.6 ac electrical characteristics (6) description symbol alt spec unit min typ max clock frequency except for read data (03h) instructions (3.0v - 3.6v) f r f c1 d.c. 1 33 mhz clock frequency except for read data (03h) instructions( 2.7v - 3.0v) f r f c 2 d.c. 104 mhz clock frequency for read data instruction ( 03h ) f r d.c. 50 mhz clock high, low time for all instructions except for read data (03h) t clh , t cll ( 1) 45% pc ns clock high, low time for read data (03h) instruction t crlh , t crll ( 1) 45% pc ns clock rise time peak to peak t clch ( 2) 0.1 v/ns clock fall time peak to peak t chcl ( 2) 0.1 v/ns /cs active setup time relative to clk t slch t css 5 ns /cs not active hold time relative to clk t chsl 5 ns data in setup time t dvch t dsu 2 ns data in hold time t chdx t dh 3 ns /cs active hold time relative to clk t chsh 3 ns /cs not active setup time relative to clk t shch 3 ns /cs deselect time (for read) t shsl 1 t csh 10 ns /cs deselect time (for erase or program or write) t shsl 2 t csh 50 ns output disable time t shqz ( 2) t dis 7 ns clock low to output valid 2.7v - 3.6v t clqv t v 6 ns output hold time t clqx t ho 1 .5 ns continued C next page ac electrical characteristics ( contd)
w25q32 jv - 63 - description symbol alt spec unit min typ max /cs high to power - down mode t dp ( 2) 3 s /cs high to standby mode without id read t res 1 ( 2) 3 s /cs high to standby mode with id read t res 2 ( 2) 1.8 s /cs high to next instruction after suspend t sus ( 2) 20 s /cs high to next instruction after reset t rst ( 2) 30 s /reset pin low period to reset the device t reset ( 2) 1 ( 3 ) s write status register time t w 10 15 ms page program time t pp 0. 7 3 ms sector erase time ( 4kb) t se 45 400 ms block erase time ( 32 kb) t be 1 120 1,600 ms block erase time (64kb) t be 2 150 2,000 ms chip erase time t ce 10 50 s notes: 1. clock high or clock low must be more than or equal to 45%pc. pc= 1/f c ( max ) . 2. value guaranteed by design and/or characterization, not 100% tested in production. 3. it s possible to reset the device with shorter t reset (as short as a few hundred ns), a 1us minimum is recommended to ensure reliable operation. 4. tested on sample basis and specified through design and characterization data. t a = 25 c, vcc = 3.0v, 25% driver strength. 5. 4 - bytes address alignment for quad read , start address from [ a1,a0 ] = ( 0,0 ).
w25q32 jv publication release date: august 30 , 2016 - 64 - revision c 9.7 serial output timing 9.8 serial input timing /cs clk io output tclqx tclqv tclqx tclqv tshqz tcll lsb out tclh msb out /cs clk io input tchsl msb in tslch tdvch tchdx tshch tchsh tclch tchcl lsb in tshsl
w25q32 jv - 65 - 10. package specificatio ns 10.1 8 - pin soic 208 - mil (package code ss) symbol millimeters inches min nom max min nom max a 1.75 1.95 2.16 0.069 0.077 0.085 a1 0.05 0.15 0.25 0.002 0.006 0.010 a2 1.70 1.80 1.91 0.067 0.071 0.075 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.19 0.20 0.25 0.007 0.008 0.010 d 5.18 5.28 5.38 0.204 0.208 0.212 d1 5.13 5.23 5.33 0.202 0.206 0.210 e 5.18 5.28 5.38 0.204 0.208 0.212 e1 5.13 5.23 5.33 0.202 0.206 0.210 e 1.27 bsc 0.050 bsc h 7.70 7.90 8.10 0.303 0.311 0.319 l 0.50 0.65 0.80 0.020 0.026 0.031 y --- --- 0.10 --- --- 0.004 0 --- 8 0 --- 8
w25q32 jv publication release date: august 30 , 2016 - 66 - revision c 10.2 8 - pin vsop 208 - mil (package code st) symbol millimeters inches min nom max min nom max a D D 1.00 D D 0.039 a1 0.05 0.10 0.15 0.002 0.004 0.006 a2 0.75 0.80 0.85 0.030 0.031 0.033 b 0.35 0.42 0.48 0.014 0.017 0.019 c 0.127 ref 0.005 ref d 5.18 5.28 5.38 0.204 0.208 0.212 e 7.70 7.90 8.10 0.303 0.311 0.319 e1 5.18 5.28 5.38 0.204 0.208 0.212 e D 1.27 D D 0.050 D l 0.50 0.65 0.80 0.020 0.026 0.031 y D D 0.10 D D 0.004 0 D 8 0 D 8
w25q32 jv - 67 - 10.3 8 - pad wson 6x5 - mm (package code zp) symbol millimeters inches min nom max min nom max a 0.70 0.75 0.80 0.028 0.030 0.031 a1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.35 0.40 0.48 0.014 0.016 0.019 c --- 0.20 ref --- --- 0.008 ref --- d 5.90 6.00 6.10 0.232 0.236 0.240 d2 3.35 3.40 3.45 0.132 0.134 0.136 e 4.90 5.00 5.10 0.193 0.197 0.201 e2 4.25 4.30 4.35 0.167 0.169 0.171 e 1.27 bsc 0.050 bsc l 0.55 0.60 0.65 0.022 0.024 0.026 y 0.00 --- 0.075 0.000 --- 0.003 note: the metal pad area on the bottom center of the package is not connected to any internal electrical signals. it can be left floating or connected to the device ground (gnd pin). avoid placement of exposed pcb vias under the pad.
w25q32 jv publication release date: august 30 , 2016 - 68 - revision c 10.4 pad xson 4 x 4x0.45 - m m (package code xg )
w25q32 jv - 69 - 10.5 16 - pin soic 300 - mil (package code sf) symbol millimeters inches min nom max min nom max a 2.36 2.49 2.64 0.093 0.098 0.104 a1 0.10 --- 0.30 0.004 --- 0.012 a2 --- 2.31 --- --- 0.091 --- b 0.33 0.41 0.51 0.013 0.016 0.020 c 0.18 0.23 0.28 0.007 0.009 0.011 d 10.08 10.31 10.49 0.397 0.406 0.413 e 10.01 10.31 10.64 0.394 0.406 0.419 e1 7.39 7.49 7.59 0.291 0.295 0.299 e 1.27 bsc 0.050 bsc l 0.38 0.81 1.27 0.015 0.032 0.050 y --- --- 0.076 --- --- 0.003 0 --- 8 0 --- 8
w25q32 jv publication release date: august 30 , 2016 - 70 - revision c 10.6 8 - pin pdip 300 - mil (package code da) symbol millimeters inches min nom max min nom max a --- --- 5.33 --- --- 0.210 a1 0.38 --- --- 0.015 --- --- a2 3.18 3.30 3.43 0.125 0.130 0.135 d 9.02 9.27 10.16 0.355 0.365 0.400 e 7.62 bsc 0.300 bsc e1 6.22 6.35 6.48 0.245 0.250 0.255 l 2.92 3.30 3.81 0.115 0.130 0.150 e b 8.51 9.02 9.53 0.335 0.355 0.375 ? 0 7 15 0 7 15 d --- 2.54 --- --- 0.100 --- w --- 1.52 --- --- 0.060 --- p --- 0.46 --- --- 0.018 --- d w p
w25q32 jv - 71 - 10.8 24 - ball tfbga 8x6 - mm (package code t b, 5x5 ball array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.26 0.3 1 0.3 6 0.010 0.012 0.014 a2 --- 0.85 --- --- 0.033 --- b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.90 8.00 8.10 0.311 0.315 0.319 d1 4.00 bsc 0.157 bsc e 5.90 6.00 6.10 0.232 0.236 0.240 e1 4.00 bsc 0.157 bsc se 1.00 typ 0.039 typ sd 1.00 typ 0.039 typ e 1.00 bsc 0.039 bsc ccc --- --- 0.10 --- --- 0.0039 note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q32 jv publication release date: august 30 , 2016 - 72 - revision c 10.9 24 - ball tfbga 8x6 - mm (package code tc, 6x4 ball array) symbol millimeters inches min nom max min nom max a --- --- 1.20 --- --- 0.047 a1 0.25 0.30 0.35 0.010 0.012 0.014 b 0.35 0.40 0.45 0.014 0.016 0.018 d 7.95 8.00 8.05 0.313 0.315 0.317 d1 5.00 bsc 0.197 bsc e 5.95 6.00 6.05 0.234 0.236 0.238 e1 3.00 bsc 0.118 bsc e 1.00 bsc 0.039 bsc note: ball land: 0.45mm. ball opening: 0.35mm pcb ball land suggested <= 0.35mm
w25q32 jv - 73 - 11. ordering information notes: 1. the w prefix is not included on the part marking. 2. only the 2 nd letter is used for the part mar king; wson package type zp is not used for the part marking. 3. standard bulk shipments are in tube (shape e). please specify alternate packing method, such as tape and reel (shape t) or tray (shape s), when placing orders. 4. for shipments with otp feature ena bled, please specify when placing orders. w (1) 25q 32 j v xx (2) i w = winbond 25 q = s pi flash serial flash memory with 4 kb sectors, dual /quad i/o 32 j = 32m - bit v = 2.7v to 3.6v ss = 8 - pin soic 208 - mil st = 8 - pin vsop 208 - mil sf = 16 - pin soic 300 - mil da = 8 - pin pdip 300 - mil zp = wson8 6x5 - mm xg = xson 4x4x0.45 - mm tb = tfbga 8x6 - mm (5x5 ball array) tc = tfbga 8x6 - mm (6x4 ball array) i = industrial ( - 40 c to +85c) ( 3,4 ) q = green package (lead - free, rohs compliant, halogen - free (tbba), antimony - oxide - free sb 2 o 3 ) with qe = 1 in status register - 2
w25q32 jv publication release date: august 30 , 2016 - 74 - revision c 11.1 valid part numbers and top side marking the following table provides the valid part numbers for the w25q32jv spiflash memory. please contact winbond for specific availability by density and package type. winbond spiflash memories use a 12 - digit product number for ordering. however, due to limited space, the top side marking on all packages uses an abbreviated 10 - digit number. package type density product number top side marking ss soic - 8 208 - mil 32m - bit w25q32jvssi q 2 5q32 j vsi q st (1) vsop - 8 208 - mil 32m - bit w25q32jvsti q 25q32j vti q sf soic - 16 300 - mil 32m - bit w25q32jvsfi q 2 5q32j vfi q da pdip - 8 300 - mil 32m - bit w25q32jvdai q 25q32j vai q zp wson - 8 6x5 - mm 32m - bit w25q32jvzpi q 25q32 j vi q xg x son - 8 4 x 4x0.45 - mm 32m - bit w 25q32jvxg i q q32 jv xgi q t b (1 ) tfbga - 24 8x6 - mm (5x5 ball array) 32m - bit w25q32jvtbiq 25q32jvbiq tc (1) tfbga - 24 8x6 - mm (6x4 ball array) 32m - bit w25q32jvtciq 25q32j vciq note: 1. these package types are special order, please contact winbond for more information.
w25q32 jv - 75 - 12. revision history version date page description a 201 4 / 06 / 3 0 new create datasheet b 2016/03/ 21 removed preliminary c 2016/ 08/3 0 4 71,73,74 added data retention description added tfbga 5x5 trademarks winbond and spiflash are trademarks of winbond electronics corporation. all other marks are the property of their respective owner. important notice winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, winbond products are not intended for applications wherein failure of winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify winbond for any damages resulting from such improper use or sales. information in this document is provided solely in connection with winbond products. winbond reserves the righ t to make changes, corrections, modifications or improvements to this document and the products and services described herein at any time, without notice.

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